File properties.h¶

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// Copyright(c) 2018-2022, Intel Corporation
//
// Redistribution  and  use  in source  and  binary  forms,  with  or  without
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//
// * Redistributions of  source code  must retain the  above copyright notice,
//   this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
// * Neither the name  of Intel Corporation  nor the names of its contributors
//   may be used to  endorse or promote  products derived  from this  software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE
// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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#pragma once
#include <opae/cxx/core/pvalue.h>
#include <opae/properties.h>

#include <iostream>
#include <map>
#include <memory>
#include <vector>

namespace opae {
namespace fpga {
namespace types {

class token;
class handle;
class properties {
 public:
  typedef std::shared_ptr<properties> ptr_t;

  const static std::vector<properties::ptr_t> none;

  properties(const properties &p) = delete;

  properties &operator=(const properties &p) = delete;

  ~properties();

  fpga_properties c_type() const { return props_; }

  operator fpga_properties() const { return props_; }

  static properties::ptr_t get();

  static properties::ptr_t get(fpga_guid guid_in);

  static properties::ptr_t get(fpga_objtype objtype);

  static properties::ptr_t get(std::shared_ptr<token> t);

  static properties::ptr_t get(fpga_token t);

  static properties::ptr_t get(std::shared_ptr<handle> h);

 private:
  properties(bool alloc_props = true);
  fpga_properties props_;

 public:
  pvalue<fpga_objtype> type;
  pvalue<uint32_t> num_errors;
  pvalue<uint16_t> segment;
  pvalue<uint8_t> bus;
  pvalue<uint8_t> device;
  pvalue<uint8_t> function;
  pvalue<uint8_t> socket_id;
  pvalue<uint32_t> num_slots;
  pvalue<uint64_t> bbs_id;
  pvalue<fpga_version> bbs_version;
  pvalue<uint16_t> vendor_id;
  pvalue<uint16_t> device_id;
  pvalue<uint16_t> subsystem_vendor_id;
  pvalue<uint16_t> subsystem_device_id;
  pvalue<char *> model;
  pvalue<uint64_t> local_memory_size;
  pvalue<uint64_t> capabilities;
  pvalue<uint32_t> num_mmio;
  pvalue<uint32_t> num_interrupts;
  pvalue<fpga_accelerator_state> accelerator_state;
  pvalue<uint64_t> object_id;
  pvalue<fpga_token> parent;
  pvalue<fpga_interface> interface;
  guid_t guid;
};

}  // end of namespace types
}  // end of namespace fpga
}  // end of namespace opae