File hello_fpga.c¶

FileList > docs > sw > samples > hello_fpga > hello_fpga.c

A code sample illustrates the basic usage of the OPAE C API. More...

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <getopt.h>
#include <unistd.h>
#include <uuid/uuid.h>
#include <opae/fpga.h>
#include <argsfilter.h>
#include "mock/opae_std.h"

Classes¶

Type	Name
struct	cache_line
struct	config

Public Attributes¶

Type	Name
struct config	config = = {
.open_flags = 0,
.run_n3000 = 0
}

Public Functions¶

Type	Name
fpga_result	find_fpga (fpga_properties device_filter, fpga_guid afu_guid, fpga_token * accelerator_token, uint32_t * num_matches_accelerators)
fpga_result	find_nlb_n3000 (fpga_handle accelerator_handle, uint64_t * afu_baddr)
void	help (void)
int	main (int argc, char * argv)
fpga_result	parse_args (int argc, char * argv)
void	print_err (const char * s, fpga_result res)
bool	probe_for_ase (void)
int	usleep (unsigned)

Macros¶

Type	Name
define	CACHELINE_ALIGNED_ADDR (p) ((p) >> LOG2_CL)
define	CL (x) ((x) * 64)
define	CSR_AFU_DSM_BASEL 0x0110
define	CSR_CFG 0x0140
define	CSR_CTL 0x0138
define	CSR_DST_ADDR 0x0128
define	CSR_NUM_LINES 0x0130
define	CSR_SRC_ADDR 0x0120
define	CSR_STATUS1 0x0168
define	DSM_STATUS_TEST_COMPLETE 0x40
define	FPGA_NLB0_UUID_H 0xd8424dc4a4a3c413
define	FPGA_NLB0_UUID_L 0xf89e433683f9040b
define	GETOPT_STRING "hscv"
define	LOG2_CL 6
define	LPBK1_BUFFER_ALLOCATION_SIZE MB(2)
define	LPBK1_BUFFER_SIZE MB(1)
define	LPBK1_DSM_SIZE MB(2)
define	MB (x) ((x) * 1024 * 1024)
define	N3000_AFUID "9AEFFE5F-8457-0612-C000-C9660D824272"
define	NLB0_AFUID "D8424DC4-A4A3-C413-F89E-433683F9040B"
define	ON_ERR_GOTO (res, label, desc)
define	TEST_TIMEOUT 30000

Detailed Description¶

The sample is a host application that demonstrates the basic steps of interacting with FPGA using the OPAE library. These steps include:

FPGA enumeration
Resource acquiring and releasing
Managing shared memory buffer
MMIO read and write

The sample also demonstrates OPAE's object model, such as tokens, handles, and properties.

The sample requires a native loopback mode (NLB) test image to be loaded on the FPGA. Refer to Quick Start Guide for full instructions on building, configuring, and running this code sample.

Public Attributes Documentation¶

variable config¶

struct config config;

Public Functions Documentation¶

function find_fpga¶

fpga_result find_fpga (
    fpga_properties device_filter,
    fpga_guid afu_guid,
    fpga_token * accelerator_token,
    uint32_t * num_matches_accelerators
)

function find_nlb_n3000¶

fpga_result find_nlb_n3000 (
    fpga_handle accelerator_handle,
    uint64_t * afu_baddr
)

function help¶

void help (
    void
)

function main¶

int main (
    int argc,
    char * argv
)

function parse_args¶

fpga_result parse_args (
    int argc,
    char * argv
)

function print_err¶

void print_err (
    const char * s,
    fpga_result res
)

function probe_for_ase¶

bool probe_for_ase (
    void
)

function usleep¶

int usleep (
    unsigned
)

Macro Definition Documentation¶

define CACHELINE_ALIGNED_ADDR¶

#define CACHELINE_ALIGNED_ADDR (
    p
) ((p) >> LOG2_CL )

define CL¶

#define CL (
    x
) ((x) * 64)

define CSR_AFU_DSM_BASEL¶

#define CSR_AFU_DSM_BASEL 0x0110

define CSR_CFG¶

#define CSR_CFG 0x0140

define CSR_CTL¶

#define CSR_CTL 0x0138

define CSR_DST_ADDR¶

#define CSR_DST_ADDR 0x0128

define CSR_NUM_LINES¶

#define CSR_NUM_LINES 0x0130

define CSR_SRC_ADDR¶

#define CSR_SRC_ADDR 0x0120

define CSR_STATUS1¶

#define CSR_STATUS1 0x0168

define DSM_STATUS_TEST_COMPLETE¶

#define DSM_STATUS_TEST_COMPLETE 0x40

define FPGA_NLB0_UUID_H¶

#define FPGA_NLB0_UUID_H 0xd8424dc4a4a3c413

define FPGA_NLB0_UUID_L¶

#define FPGA_NLB0_UUID_L 0xf89e433683f9040b

define GETOPT_STRING¶

#define GETOPT_STRING "hscv"

define LOG2_CL¶

#define LOG2_CL 6

define LPBK1_BUFFER_ALLOCATION_SIZE¶

#define LPBK1_BUFFER_ALLOCATION_SIZE MB (2)

define LPBK1_BUFFER_SIZE¶

#define LPBK1_BUFFER_SIZE MB (1)

define LPBK1_DSM_SIZE¶

#define LPBK1_DSM_SIZE MB (2)

define MB¶

#define MB (
    x
) ((x) * 1024 * 1024)

define N3000_AFUID¶

#define N3000_AFUID "9AEFFE5F-8457-0612-C000-C9660D824272"

define NLB0_AFUID¶

#define NLB0_AFUID "D8424DC4-A4A3-C413-F89E-433683F9040B"

define ON_ERR_GOTO¶

#define ON_ERR_GOTO (
    res,
    label,
    desc
) do {                                       \
        if ((res) != FPGA_OK ) {            \ print_err ((desc), (res));  \
            goto label;                \
        }                                  \
    } while (0)

define TEST_TIMEOUT¶

#define TEST_TIMEOUT 30000

The documentation for this class was generated from the following file docs/sw/samples/hello_fpga/hello_fpga.c