File manage.h¶
File List > docs > sw > include > opae > manage.h
Go to the documentation of this file.
// Copyright(c) 2017, Intel Corporation
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of Intel Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
#ifndef __FPGA_MANAGE_H__
#define __FPGA_MANAGE_H__
#include <opae/types.h>
#ifdef __cplusplus
extern "C" {
#endif
fpga_result fpgaAssignPortToInterface(fpga_handle fpga,
uint32_t interface_num,
uint32_t slot_num,
int flags);
fpga_result fpgaAssignToInterface(fpga_handle fpga,
fpga_token accelerator,
uint32_t host_interface,
int flags);
fpga_result fpgaReleaseFromInterface(fpga_handle fpga,
fpga_token accelerator);
fpga_result fpgaReconfigureSlot(fpga_handle fpga,
uint32_t slot,
const uint8_t *bitstream,
size_t bitstream_len, int flags);
#ifdef __cplusplus
} // extern "C"
#endif // __cplusplus
#endif // __FPGA_MANAGE_H__