FPGA Developer Journey Guide: Open FPGA Stack¶
Last updated: February 26, 2025
1 Introduction¶
This document is intended to help you understand the FPGA developer flow using OFS as well as considerations you should take when creating your custom platform.
After reviewing the document, you shall be able to:
- Understand how to evaluate the OFS framework for your platform needs.
- Select a starting shell or FIM to begin your work.
- Understand what resources are available for guiding you through making modifications for custom design as well as simulation and debug.
The general development flow is depicted in the diagram below and discussed in more detail in each section of this document.
Figure 1-1: FPGA Developer Flow
2 Evaluate OFS¶
The repositories in the OFS site are tagged in the format <yyyy>.<release>-<iteration> based on the version of Quartus that is used for each release. For example, a tag of 2024.3-1 indicates the 1st release of OFS that uses Quartus® Prime Pro Edition Version 24.3. If there are any updates to a particular release package using the same version of Quartus, the last number will be incremented by 1, for example, 2024.3-2 would indicate the 2nd release of OFS that uses Quartus® Prime Pro Edition Version 24.3.
By clicking on the release link to the right of the RTL repositories, you will find the latest release, the tag number and release notes.
Figure 2-1: OFS Repository Release Page Link
By scrolling to the end of the release page, you will find assets attached to the release that you can leverage for quick evaluation of OFS, such as FPGA binary files, POF and SOF as well as a sample AFU and a partial reconfiguration directory for building your own custom workload.
There are two ways to evaluate OFS depending on your needs:
Option 1: Setup your card and software in a server using the steps provided in one of the corresponding Getting Started Guides and leverage the appended binaries in the FIM RTL repository release page "Assets" tab to preview the software and design functionality the OFS framework provides you out of the box. This step will give you a good high-level overview of OFS. Getting Started Guides are available for the following FIM(shell) designs:
- Getting Started Guide: OFS for Agilex™ 7 PCIe Attach FPGAs (Intel® FPGA SmartNIC N6001-PL/N6000-PL)
- Getting Started Guide: OFS for Agilex™ 7 PCIe Attach FPGAs (F-Series Development Kit (2xF-Tile))
- Getting Started Guide: OFS for Agilex™ 7 PCIe Attach FPGAs (I-Series Development Kit (2xR-Tile, 1xF-Tile))
- Getting Started Guide: OFS for Agilex™ 7 SoC Attach FPGAs
- Getting Started Guide: OFS for Stratix 10® FPGA PCIe Attach FPGAs
Option 2: After your card and software are installed using the steps provided in one of the corresponding Getting Started Guides listed above, use a corresponding Evaluation Guide and provided evaluation script to run through all the capabilities of the OFS framework by selecting one of the choices in the evaluation menu. The evaluation script gives you familiarity of the entire design, build, simulation, programming and test flow for OFS, including a OneAPI flow.
- Automated Evaluation User Guide: OFS for Agilex™ 7 PCIe Attach FPGAs
- Automated Evaluation User Guide: OFS for Agilex™ 7 SoC Attach FPGAs
- Automated Evaluation User Guide: OFS for Stratix® 10 PCIe Attach FPGAs
The scripts that go with each user guide are found in the assets tab of the corresponding FIM RTL repository's latest tag release page.
To use the full functionality of the script you will want to ensure you clone all of the appropriate repositories below at the same level just under an OFS directory you create, such as ofs-2024.3, similar to the figure below.
Figure 2-2: Directory Structure of Cloned Repositories
##|-- ofs-2024.3
##| |--examples-afu
##| |--linux-dfl-backport
##| |--ofs-agx7-pcie-attach
##| |--ofs-oneapi-asp
##| |--opae-sdk
##| |--opae-sim
##| |--ofs-agx7-pcie-attach_eval.sh
You can access the repositories from ofs.github.io by clicking on the GitHub icon in the right corner of the site.
Figure 2-3: OFS Site Link from ofs.github.io
Clone one of the FIM RTL repositories you intend to use:
-
Make a top level directory
-
Initialize repository
-
Select a FIM RTL repository to clone
-
To clone Agilex™ 7 PCIe Attach FIM RTL repository
-
To clone Agilex™ 7 SoC Attach FIM RTL Repository
-
To clone Intel Stratix 10 PCIe Attach FIM RTL Repository
-
After cloning your FIM RTL repository, clone the other necessary repositories:
-
Clone the
linux-dfl-backportrepository -
Clone the
opae-sdkrepository-
Use the following commands for all PCIe Attach Cards
-
Use the following commands for the SoC Attach Card
-
-
Clone the
oneapi-asprepository if OneAPI support is required. -
Clone the
ofs-platform-afu-bbbrepository -
Clone the
opae-simrepository -
Clone the
examples-afurepository
You will also want to ensure you install the correct version of Intel Quartus Prime Pro as directed in the release notes in addition to any Quartus patches. Note that Quartus Prime Pro software can be downloaded from the downloads tab on intel.com. Quartus Prime Pro patches required are attached to the assets tab at the bottom of the tagged RTL repository release page.
3 Select a Starting Shell/FIM¶
To begin your development, start with an existing shell that most closely matches your device and end solution. The OFS site has both Agilex™ 7 and Stratix 10 FPGA reference designs you can use as a starting point for your own design. These designs can be ported to different device OPNs if a different resource utilization is required.
To begin you may want to learn more about Intel Stratix 10 and Agilex™ 7 family offerings. Please refer to the following links:
Note that each reference design provides an integrated shell, called the FPGA Interface Manager (FIM), which is encompasses in blue in the diagrams below. This shell provides standard AXI interfaces to the Accelerator Functional Unit (AFU) region, shown in green, which depicts a region where a workload or partial reconfiguration slot resides. The regions are not drawn to scale. The figures and tables below give an overview of the available starting points for your design.
Figure 3-1: OFS FIM Targeting Agilex®7 PCIe Attach (P-tile, E-tile)
| Key Feature | Description |
|---|---|
| Target OPN | • AGFB014R24A2E2V |
| PCIe | • P-tile PCIe* Gen4x16 |
| Virtualization | • 5 physical functions/3 virtual functions with ability to expand |
| Memory | 5 DDR Channels: • One HPS DDR4 bank, x40 (x32 Data and x8 ECC), 1200 MHz, 1GB each • Four Fabric DDR4 banks, x32 (no ECC), 1200 MHz, 4GB |
| Ethernet | Provided configurations: • 2x4x25GbE • 2x4x10GbE • 2x100GbE |
| Hard Processor System | • 64-bit quad core Arm® Cortex®-A53 MPCore with integrated peripherals. |
| Configuration and Board Manageability | • FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration) • Platform Controller Management Interface (PMCI) Module for Board Management Controller |
| Partial Reconfiguration | • Supported |
| OneAPI[1] | • OneAPI Acceleration Support Package (ASP) provided with compiled FIM to support OneAPI Runtime |
| Software Support | • Linux DFL drivers targeting OFS FIMs • OPAE Software Development Kit • OPAE Tools |
| Target Board | • Intel® FPGA SmartNIC N6001-PL |
[1] OFS version 2024.2-1 is the latest version of OFS that supports OneAPI. Please use this version of OFS if OneAPI support is required.
Click here for the OFS Collateral for Agilex™ 7 FPGA PCIe Attach Reference FIM documentation collection.
Figure 3-2: OFS FIM Targeting Agilex®7 PCIe Attach (2xF-tile)
| Key Feature | Description |
|---|---|
| Target OPN | • AGFB027R24C2E2VR2 |
| PCIe | • F-tile PCIe* Gen4x16 |
| Virtualization | • 5 physical functions/3 virtual functions with ability to expand |
| Memory | 3 DDR Channels: • One HPS DDR4 bank, x40 (x32 Data and x8 ECC), 2400 MHz, 1GB each • Two Fabric DDR4 banks, x64 (no ECC), 2400 MHz, 8GB |
| Ethernet | • 2x4x25GbE |
| Hard Processor System | • 64-bit quad core Arm® Cortex®-A53 MPCore with integrated peripherals. |
| Configuration and Board Manageability | • FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration) |
| Partial Reconfiguration | • Supported |
| OneAPI[1] | • OneAPI Acceleration Support Package (ASP) provided with compiled FIM to support OneAPI Runtime |
| Software Support | • Linux DFL drivers targeting OFS FIMs • OPAE Software Development Kit • OPAE Tools |
| Target Board | • Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) |
[1] OFS version 2024.2-1 is the latest version of OFS that supports OneAPI. Please use this version of OFS if OneAPI support is required.
Click here for the OFS Collateral for Agilex™ 7 FPGA PCIe Attach Reference FIM documentation collection.
Figure 3-3: OFS FIM Targeting Agilex®7 PCIe Attach (2xR-tile, F-tile)
| Key Feature | Dscription |
|---|---|
| Target OPN | • AGIB027R29A1E1VB |
| PCIe | • R-tile PCIe Gen5x16 • R-tile PCIe 2xGen5x8 • R-tile PCIe Gen4x16 |
| Virtualization | • 5 physical functions/3 virtual functions with ability to expand |
| Memory | • Four Fabric DDR4 channels consisting of: • Two x64 (no ECC), 2666 MHz, 8GB Component memory • Two x64 (no ECC), 2666 MHz, 8GB UDIMM memory OR • Three Fabric DDR4 channels consisting of: • Two x64 (no ECC), 2666 MHz, 8GB Component memory • One x64 (no ECC), 2666 MHz, 8GB RDIMM memory |
| Ethernet | • 2x4x25GbE • 2x200GbE • 2x400GbE |
| Hard Processor System | • Not enabled |
| Configuration and Board Manageability | • FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration) |
| Partial Reconfiguration | • Supported |
| OneAPI[1] | • OneAPI Acceleration Support Package (ASP) provided with compiled FIM to support OneAPI Runtime |
| Software Support | • Linux DFL drivers targeting OFS FIMs • OPAE Software Development Kit* OPAE Tools |
| Target Board | • Agilex™ 7 FPGA I-Series Development Kit (2x R-Tile and 1xF-Tile) |
[1] OFS version 2024.2-1 is the latest version of OFS that supports OneAPI. Please use this version of OFS if OneAPI support is required.
Click here for the OFS Collateral for Agilex™ 7 FPGA PCIe Attach Reference FIM documentation collection.
Figure 3-4: OFS FIM Features Targeting Agilex® 7 SoC Attach
| Key Feature | Description |
|---|---|
| Device OPN | AGFC023R25A2E2VR0 |
| PCIe | • P-tile PCIe* Gen4x16 to the Host • P-tile PCIe* Gen4x16 to the SoC (IceLake-D) |
| Virtualization | • Host: 2 physical functions • SoC: 1 physical function and 3 Virtual functions |
| Memory | • Four Fabric DDR4 banks, x40 (optional ECC, be configured as x32 and ECC x8 ), 1200 MHz, 4GB |
| Ethernet | • 2x4x25GbE |
| Configuration and Board Manageability | • FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration) • Platform Controller Management Interface (PMCI) Module for Board Management Controller |
| Partial Reconfiguration | • Supported |
| Software Support | • Linux DFL drivers targeting OFS FIMs • OPAE Software Development Kit• OPAE Tools |
| Target Board | • Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL |
Note: Source code for BMC RTL/Firmware that works with this reference FIM can be obtained by contacting your Intel Sales Representative.
Click here for the OFS Collateral for Agilex™ SoC Attach Reference FIM documentation collection.
Figure 3-5: OFS FIM Targeting Stratix® 10 FPGA PCIe Attach
| Key Feature | Description |
|---|---|
| Device OPN | • 1SX280HN2F43E2VG |
| Ethernet Configuration | • 1x10GbE example with 2x100GbE capability |
| PCIe | • Gen3x16 |
| EMIF | • Up to four DDR channels |
| PF/VF | • 1 PF/3 VFs |
| Management | • FPGA Management Engine (FME) with FIM management registers |
| Interface | • Arm® AMBA®4 AXI Interface |
| HLD support | • oneAPI |
| Software | • Kernel code upstreamed to Linux.org |
| Target Board | • Intel® FPGA Programmable Acceleration Card D5005 |
Click here for the OFS Collateral for Stratix® 10 FPGA PCIe Attach Reference FIM documentation.
4 Review Release Notes¶
Before beginning your design, read the release notes for each repository you are using by selecting the appropriate release tag found by clicking on the "Release" link to the right of the corresponding repository. The release page may also have assets appended such as useful binaries, patches or scripts.
5 Setup Your Environment For Development¶
When you are ready to begin development you will want to ensure you have any other setup requirements satisfied by reviewing instructions in the corresponding FIM Developer Guide and if you are implementing a OneAPI Board Support Package, the oneAPI ASP Getting Started User Guide as well.
- Shell Developer Guide: OFS for Agilex™ 7 PCIe Attach (2xR-tile, F-tile) FPGAs * Can be used with Agilex™ 7 FPGA R-Series Development Kit (2xR-Tile, 1xF-Tile)
- Shell Developer Guide: OFS for Agilex™ 7 PCIe Attach (2xF-tile) FPGAs * Can be used with Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile)
- Shell Developer Guide: OFS for Agilex™ 7 PCIe Attach (P-tile, E-tile) FPGAs * Can be used with Intel® FPGA SmartNIC N6001-PL
- Shell Developer Guide: OFS for Agilex™ 7 SoC Attach FPGAs * Can be used with Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL
- Shell Developer Guide: OFS for Stratix® 10 PCIe Attach FPGAs * Can be used with Intel® FPGA PAC D5005
For oneAPI setup:
- oneAPI Accelerator Support Package (ASP): Getting Started User Guide
* Can be used with:
- Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) - Intel® FPGA SmartNIC N6001-PL
6 Customize Your Shell, Build and Debug¶
For your own custom design, you may need to:
- Target the OFS reference design to a different device
- Modify the pin assignments
- Modify or remove existing peripheral IP
- Add new interface IP
- Repartition the partial reconfiguration region
The FIM Developer Guides for each reference FIM show you how to make these changes and provide steps on how to run unit simulation or add SignalTap to your design for debugging.
If you are also interested in testing different examples for the Acceleration Functional Unit (AFU) or workload region of your design or creating your own AFU design, you can refer to the corresponding AFU Developer Guides:
- Workload Developer Guide: OFS for Agilex™ 7 PCIe Attach FPGAs
- Workload Developer Guide: OFS for Agilex™ 7 SoC Attach FPGAs
- Workload Developer Guide: OFS for Stratix® 10 PCIe Attach FPGAs
7 Simulate and Debug¶
Setup and test files to perform system-level Universal Verification Methodology (UVM) testing are provided in each FIM RTL repository. Please refer to the corresponding UVM Simulation User Guide for details on test bench architecture, setup and testing.
- UVM Simulation User Guide: OFS for Agilex™ 7 PCIe Attach
- UVM Simulation User Guide: OFS for Agilex™ 7 SoC Attach
- UVM Simulation User Guide: OFS for Stratix® 10 PCIe Attach
Note: UVM simulation is not supported for OFS designs using R-Tile devices, such as the Agilex™ 7 FPGA I-Series Development Kit (2x R-Tile and 1xF-Tile).
8 Optional: Build OneAPI Accelerator Support Package (ASP)¶
If you are considering providing oneAPI support for your custom board design, you must integrate the oneAPI ASP hardware and software components into your design. Reference the following documents to learn about the architecture and implementation flow for the oneAPI ASP with an OFS design.
- oneAPI Accelerator Support Package (ASP): Getting Started User Guide
- oneAPI Accelerator Support Package(ASP) Reference Manual: Open FPGA Stack
9 Optional: Driver or OFS Software Tool Modifications¶
As you add or remove interfaces to your custom design, you may need to modify or enhance existing drivers that accompany the OFS reference design. Additionally, you may decide you want to create additional utilities or plugins leveraging the OFS software infrastructure. In this case, refer to the Software Reference Manual: Open FPGA Stack to learn more about the underlying driver and software architecture and how to make modifications.
Additionally, for guidance on using a Kernel-based Virtual Machine with OFS, refer to our KVM User Guide.
KVM User Guide: Open FPGA Stack
10 Test and Deploy¶
When testing and deploying your platform you are encouraged to modify and tailor the evaluation scripts you used in Section 2 to assist in automating your continuous integration flow. You may also want to refer to our Docker User Guide to understand how to use Docker for Development and Deployment.
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