Open FPGA Stack Overview¶
Open FPGA Stack (OFS): OFS is an open-source hardware and software framework that reduces the development time for creating your custom platform. Provided within this framework are reference designs targeting different Intel® FPGA devices with upstreamed drivers and management software tools.
The reference shells, called FPGA Interface Manager (FIMs), provide an integrated, timing closed design with the most common interfaces for host attach applications. After selecting your starting shell, you can add or subtract interfaces depending on your application requirements. Then leverage the build scripts, RTL, unit tests, Universal Verification Methodology (UVM) environment, software and drivers for this reference shell as a starting point for your own FPGA platform solution.
OFS currently targets Intel Stratix® 10 and Intel Agilex™ FPGA Device Families.
To find out more about Intel FPGAs, visit the Intel Stratix 10 and Intel Agilex pages at Intel.com.
How Can I Start Using OFS?¶
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If you are interested in a production card that uses OFS for your workload application development or for full deployment, please refer to the OFS Board Catalog.
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If you are an FPGA developer, refer to our [FPGA Developer Journey Guide]. FPGA Developers interested in oneAPI should reference this guide as well.
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If you are a software developer, refer to our Software Tab for driver and user space tool development resources.
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If you are an application developer, preview our overview video on how OFS can help you develop FPGA-based workloads and review one of the AFU Developer Guides to find the OFS resources available for creating your own application workload.
- Accelerator Functional Unit (AFU) Developer Guide: OFS for Intel® Agilex® 7 PCIe Attach
- Accelerator Functional Unit (AFU) Developer Guide: OFS for Intel® Agilex® 7 SoC Attach
- Accelerator Functional Unit (AFU) Developer Guide: OFS for Intel® Stratix® 10 FPGA PCIe Attach
Beyond the resources we have on this site, you can navigate to the OFS GitHub repos by clicking the GitHub repository icon at the top left corner of this site page.
What FIM Reference Designs Are Available?¶
Below details the four current reference designs (aka FIMs) you can choose from:
OFS FIM Targeting Intel® Agilex®7 PCIe Attach (P-tile, E-tile)
| Key Feature | Description |
|---|---|
| Target OPN | AGFB014R24A2E2V |
| PCIe | P-tile PCIe* Gen4x16 |
| Virtualization | 5 physical functions/3 virtual functions with ability to expand |
| Memory | 5 DDR Channels:* One HPS DDR4 bank, x40 (x32 Data and x8 ECC), 1200 MHz, 1GB each* Four Fabric DDR4 banks, x32 (no ECC), 1200 MHz, 4GB |
| Ethernet | 2x4x25GbE, 2x4x10GbE or 2x100GbE |
| Hard Processor System | 64-bit quad core Arm® Cortex®-A53 MPCore with integrated peripherals. |
| Configuration and Board Manageability | * FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration) * Platform Controller Management Interface (PMCI) Module for Board Management Controller |
| Partial Reconfiguration | Supported |
| OneAPI | OneAPI Acceleration Support Package (ASP) provided with compiled FIM to support OneAPI Runtime |
| Software Support | * Linux DFL drivers targeting OFS FIMs * OPAE Software Development Kit* OPAE Tools |
| Target Board | Intel® FPGA SmartNIC N6001-PL |
Click here for the OFS Collateral for Intel® Agilex® PCIe Attach Reference FIM documentation collection.
OFS FIM Targeting Intel® Agilex®7 PCIe Attach (2xF-tile)
| Key Feature | Description |
|---|---|
| Target OPN | AGFB027R24C2E2VR2 |
| PCIe | F-tile PCIe* Gen4x16 (currently downtrains to Gen4x8 in the ES version of the development kit) |
| Virtualization | 5 physical functions/3 virtual functions with ability to expand |
| Memory | 3 DDR Channels:* One HPS DDR4 bank, x40 (x32 Data and x8 ECC), 2400 MHz, 1GB each* Two Fabric DDR4 banks, x64 (no ECC), 2400 MHz, 8GB |
| Ethernet | 2x4x25GbE |
| Hard Processor System | 64-bit quad core Arm® Cortex®-A53 MPCore with integrated peripherals. |
| Configuration and Board Manageability | * FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration) * Platform Controller Management Interface (PMCI) Module for Board Management Controller |
| Partial Reconfiguration | Supported |
| OneAPI | OneAPI Acceleration Support Package (ASP) provided with compiled FIM to support OneAPI Runtime |
| Software Support | * Linux DFL drivers targeting OFS FIMs * OPAE Software Development Kit* OPAE Tools |
| Target Board | Intel Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) |
Click here for the OFS Collateral for Intel® Agilex® PCIe Attach Reference FIM documentation collection.
OFS FIM Features Targeting Intel® Agilex® 7 SoC Attach
| Key Feature | Description |
|---|---|
| Device OPN | AGFC023R25A2E2VR0 |
| PCIe | P-tile PCIe* Gen4x16 to the Host P-tile PCIe* Gen4x16 to the SoC (IceLake-D) |
| Virtualization | Host: 2 physical functions SoC: 1 physical function and 3 Virtual functions |
| Memory | Four Fabric DDR4 banks, x40 (optional ECC, be configured as x32 and ECC x8 ), 1200 MHz, 4GB |
| Ethernet | 2x4x25GbE |
| Configuration and Board Manageability | * FPGA Management Engine that provides general control of common FPGA tasks (ex. error reporting, partial reconfiguration) * Platform Controller Management Interface (PMCI) Module for Board Management Controller |
| Partial Reconfiguration | Supported |
| Software Support | * Linux DFL drivers targeting OFS FIMs * OPAE Software Development Kit * OPAE Tools |
| Target Board | Intel® Infrastructure Processing Unit (Intel® IPU) Platform F2000X-PL |
Note: Source code for BMC RTL/Firmware that works with this reference FIM can be obtained by contacting your Intel Sales Representative.
Click here for the OFS Collateral for Intel® Agilex® SoC Attach Reference FIM documentation collection.
OFS FIM Targeting Intel® Stratix® 10 FPGA PCIe Attach
| Key Feature | Intel Stratix 10 Reference FIM |
|---|---|
| Device OPN | 1SX280HN2F43E2VG |
| Ethernet Configuration | 1x10GbE example with 2x100GbE capability |
| PCIe | Gen3x16 |
| EMIF | Up to four DDR channels |
| PF/VF | 1 PF/3 VFs |
| Management | FPGA Management Engine (FME) with FIM management registers |
| Interface | Arm® AMBA®4 AXI Interface |
| HLD support | oneAPI |
| Software | Kernel code upstreamed to Linux.org |
| Target Board | Intel® FPGA Programmable Acceleration Card D5005 |
Click here for the OFS Collateral for Intel® Stratix® 10 FPGA PCIe Attach Reference FIM documentation.
To find information on the latest releases, go to the Discussions Tab in the OFS GitHub repository.
Open FPGA Stack Repositories¶
Accessing OFS ingredients to use within the development framework is easy. The github.com/OFS site provides all the hardware and software repositories in one location.
| Development Focus | Repository Folder | Description |
|---|---|---|
| Hardware | ofs-agx7-pcie-attach | Provides RTL, unit tests, and build scripts to create an Intel® Agilex® 7 FIM and is leveraged as a starting point for a custom PCIe Attach design. The reference FIM targets an Intel® FPGA SmartNIC N6001-PL Platform or the Intel Agilex 7 FPGA F-Series Development Kit (2x F-Tile) User Guide. |
| Hardware | ofs-f2000x-pl | Provides RTL, unit tests, and build scripts to create Intel®Agilex® FIM and is leveraged as a starting point for a custom SoC Attach design. The reference FIM targets an Intel® FPGA IPU F2000X-PL Platform. |
| Hardware | ofs-d5005 | Provides RTL, unit tests, and build scripts to create Intel® Stratix 10® FIM and is leveraged as a starting point for a custom PCIe Attach design. The reference FIM targets an Intel® FPGA PAC D5005 development board. |
| Hardware | oneapi-asp | Contains the files to generate the support package that works with the reference shells and allows you to use OneAPI. This is an optional repository for developers interested in OneAPI |
| Hardware | ofs-fim-common | Provides RTL components that are shared among all new platforms that are introduced in OFS. This folder is a subumodule in each platform repository folder. |
| Hardware | examples-afu | Provides simple Accelerator Functional Unit (AFU) examples you can use as a template for starting your own workload design. |
| Hardware | ofs-platform-afu-bbb | Contains the hardware code to build a standard interface between the FIM and your workload. |
| Software | linux-dfl | This repository is a mirror of the linux.org Git site and contains the most up-to-date drivers that are being developed and upstreamed for OFS platforms. |
| Software | meta-ofs | This repository provides the Linux® DFL kernel and the OPAE SDK for the Yocto® Project. |
| Software | opae-sdk | Contains the ingredients to build the OFS Open Programmable Acceleration Engine (OPAE) Software Development Kit which provides APIs and userspace tools for OFS FPGA management. |
| Software | opae-sim | This repository is used to build the AFU Hardware/Software Co-Simulation Environment workload developers can use to ensure their AFU can work with the OFS software stack. |
| Software | linux-dfl-backport | A place for finding and leveraging out-of-tree backported drivers for older OS versions . |
| Software | opae-legacy | Supports OFS platforms built on the legacy version of OPAE software. Not used in current OFS designs |
| Documentation | ofs.github.io | Contains the hardware and software collateral that surfaces on the OFS website: https://ofs.github.io |